1. Field of the Invention
The present invention relates to a semiconductor device and to a method of manufacturing the same and, more particularly, to a semiconductor device including a capacitor having a ferroelectric layer or a high-dielectric layer and to a method of manufacturing the same.
2. Description of the Related Art
The flash memory, the ferroelectric memory (FeRAM), etc. are known, as the nonvolatile memory that can still store the information after the power supply is turned off.
The flash memory has such a structure that the information are stored by accumulating charges in the floating gate that is buried in the gate insulating film of the insulated-gate field effect transistor (IGFET). The tunnel current that passes through the insulating film formed between the floating gate and the semiconductor substrate must be supplied to write or erase the information, and thus the high voltage is needed to write or erase the information.
The FeRAM has the ferroelectric capacitor and stores the information by using the hysteresis characteristic of the ferroelectric substance. The ferroelectric capacitor has a structure in which the ferroelectric film is put between a pair of electrodes. Such ferroelectric capacitor generates the polarization in response to the applied voltage between the electrodes and has the spontaneous polarization after the applied voltage is removed. If the polarity of the applied voltage is inverted, the polarity of the spontaneous polarization is also inverted. The information can be read by detecting the spontaneous polarization.
Accordingly, the FeRAM can be driven by the low voltage rather than the flash memory and thus can execute the high-speed writing by the saved power.
The FeRAM includes the MOSFET and the ferroelectric capacitor in the memory cell region. The ferroelectric capacitor is formed on the first insulating film, that covers the MOSFET formed on the semiconductor substrate, and is covered with the second insulating film. Various structures for connecting the ferroelectric capacitor and the MOSFET have been proposed.
For example, in Patent Application Publication (KOKAI) Hel 11-238855, the FeRAM manufacturing method is set forth which includes the steps of forming the first and second contact holes, that expose the upper electrode and the lower electrode of the capacitor, respectively, on the second insulating film covering the capacitor, then filling the conductive pattern in the first and second contact holes, then forming the third contact hole, that exposes the impurity diffusion layer, in the first insulating film covering the MOSFET, then filling the plug into the third contact hole, and then connecting the conductive pattern in the first contact hole and the plug in the third contact hole by the wiring.
In order to connect electrically the impurity diffusion layer of the MOSFET and the upper electrode of the capacitor, such FeRAM has the plug on the impurity diffusion layer of the MOSFET, the conductive pattern on the capacitor, and the wiring for connecting them. Thus, the structure becomes complicated and thus a number of manufacturing steps are requested.
In the FeRAM, in order to reduce the damage of the ferroelectric capacitor, it is preferable that the number of steps necessary for the connection between the ferroelectric capacitor and the MOSFET should be reduced.
On the contrary, in FIG. 3 of Patent Application Publication (KOKAI) 2000-36568, the FeRAM is set forth which has the structure including the first insulating film for covering the MOSFET, the ferroelectric capacitor formed on the first insulating film, and the second insulating film for covering the ferroelectric capacitor, whereby the impurity diffusion layer of the MOSFET and the upper electrode of the ferroelectric capacitor are connected by one plug formed the first and second insulating films and the wiring formed on the second insulating film.
According to this, throughput can be improved by simplifying the connecting structure between the MOSFET and the capacitor.
In the meanwhile, in the FeRAM set forth in Patent Application Publication (KOKAI) 2000-36568, the wiring structure for leading the lower electrode of the capacitor is not set forth. But it is preferable that the wiring structure connected to the lower electrode should be much more simplified.
As set forth in Patent Application Publication (KOKAI) Hei 11-238855, there may be considered the wiring connection to the lower electrode of the capacitor such that the holes are formed simultaneously on the lower electrode and the upper electrode of the capacitor and then the wiring is connected to the lower electrode via these holes.
However, in the case that the surface of the insulating film covering the capacitor is flat, depths of the hole formed on the lower electrode and the hole formed on the upper electrode become different. Therefore, if it is attempted to form simultaneously these holes, there is such a possibility that, because the hole formed on the upper electrode is formed early, the underlying ferroelectric film is damaged.